In the technologies of micro-projection displays, e.g., a transmissive Liquid Crystal Display (LCD), a reflective Digital Light Processor (DLP), a reflective Liquid Crystal On Silicon (LCOS), etc., or in the technologies of flat panel displays, e.g., a liquid crystal display, an Organic Light Emitting Diode (OLED) display, an electrophoresis display, a Plasma Display Panel (PDP), etc., pixel units of a display matrix (or referred to as electro-controlled optical modulation units) are gated row by row or every other row by a row drive signal and performs display in response to a column data signal.
FIG. 1 illustrates a circuit diagram of a display matrix of a liquid crystal display device in the conventional art. The display matrix includes M×N pixel units (M and N are natural numbers), where M is the number of rows and N is the number of columns. Only two rows multiplied by two columns of the pixel units are schematically illustrated in FIG. 1.
As illustrated in FIG. 1, each pixel unit includes a switch element T1, a storage capacitor Cst and a pixel capacitor Clc. The switch element T1 has a gate coupled with a corresponding row line, a source coupled with a corresponding column line, and a drain coupled with the storage capacitor Cst and the pixel capacitor Clc. Specifically, a switch element T1 of a pixel unit p11 has a gate coupled with a row line L1 and a source coupled with a column line R1; a switch element T1 of a pixel unit p12 has a gate coupled with the row line L1 and a source coupled with a column line R2; a switch element T1 of a pixel unit p21 has a gate coupled with a row line L2 and a source coupled with the column line R1; and a switch element T1 of a pixel unit p22 has a gate coupled with the row line L2 and a source coupled with the column line R2.
When the pixel units p11 and p12 are gated by a gate drive signal G1 on the row line, L1, the switch elements T1 of the pixel units p11 and p12 are closed, and column data signals D1 and D2 on the column lines R1 and R2 are applied respectively to the storage capacitors Cst and the pixel capacitors Clc of the pixel units p11 and p12 via the switch elements T1. When the pixel units p21 and p22 are gated by a gate drive signal G2 on the row line L2, the switch elements T1 of the pixel units p21 and p22 are closed, and the column data signals D1 and D2 on the column lines R1 and R2 are applied respectively to the storage capacitors Cst and the pixel capacitors Clc of the pixel units p21 and p22 via the switch elements T1.
When a column data signal is applied to the storage capacitor Cst and the pixel capacitor Clc the storage capacitor Cst is charged to retain the voltage of the column data signal and provides the voltage to the pixel capacitor Clc, liquid crystal molecules LC filled between both electrodes of the pixel capacitor Clc are twisted to an extent which is determined by the voltage of the column data signal, and to an extent which can generate intensity varying light in combination with a backlight source, a polarization piece, etc.
Typically, the switch elements of the pixel units as illustrated in FIG. 1 are transistors, e.g., thin film transistors, field effect transistors, etc., which may have to occupy an indispensable layout area and thus hinder miniaturization and high level of integration of the display device due to process factors of, e.g., a design rule, a Critical Dimension (CD), a layout, etc., resulting from the gates, sources and drains of the transistors, etc.